"Government Notifies Semicon 2.0 Framework for Domestic Chip Design Push"
Fabless company
a firm that designs and sells chips but outsources physical chip fabrication to foundries.
System-on-Chip (SoC)
a single integrated circuit that combines a processor, memory, and other components for a complete function.
Semiconductors are the foundational components of virtually every modern electronic device, from smartphones and defence systems to medical equipment and automobiles. A country's ability to design and manufacture chips is a matter of both economic competitiveness and national security. India historically relied almost entirely on chip imports. This dependence became a serious vulnerability during the global semiconductor shortage that disrupted automobile and electronics production worldwide.
To address this, the government launched the India Semiconductor Mission (ISM) under the Semicon India Programme, structured as a specialised division within the Digital India Corporation under the Ministry of Electronics and Information Technology (MeitY). The first programme offered fiscal support for chip fabrication, Assembly, Testing, Marking and Packaging (ATMP), and design. It also prioritised talent development, recognising that hardware capability requires trained engineers, not just capital. The first programme resulted in approvals for 12 manufacturing projects, including facilities by Micron and Tata Electronics.
Globally, this policy push is part of a wider reassertion of industrial policy in strategic technology. The United States enacted the CHIPS and Science Act, the European Union launched its European Chips Act, and Japan, South Korea, and Taiwan have all deepened state support. India's semiconductor policy trajectory sits within this worldwide trend.
Semicon 2.0 is the upgraded semiconductor policy framework, formally notified in August 2026. It is structured around six pillars and ten categories covering the full semiconductor value chain. The nodal agency remains ISM under MeitY, with the Centre for Development of Advanced Computing (C-DAC) assisting specifically on design categories.
Pillar 1 (Design) is the centrepiece of the new programme. It has three tracks. The first targets chips for national security and critical infrastructure, compute, memory, radio frequency, power, networking, and sensors. Companies in this track must be incorporated, headquartered, and substantially staffed in India, and owned and controlled by Indian citizens. They may work in consortiums with global partners. C-DAC will invite bids, provide financial support and design infrastructure, and jointly own the resulting intellectual property. The second track supports commercial chip-design companies. Start-ups and MSMEs can receive milestone-linked seed funding of up to Rs 15 crore or 50% of project cost, whichever is lower. Larger companies can opt for royalty financing, repaying 5% of net revenue until 1.5 times the government assistance is recovered. …
Discuss the rationale of the Production Linked Incentive (PLI) scheme. What are its achievements? In what way can the functioning and outcomes of the scheme be improved?
'Investment in infrastructure is essential for more rapid and inclusive economic growth.' Discuss in the light of India's experience.
What is the status of digitalization in the Indian economy? Examine the problems faced in this regard and suggest improvements.
Consider the following statements regarding the Semicon 2.0 programme notified by the Government of India:
1.The programme is structured around six pillars and ten categories.
2.The Deployment-Linked Incentive reimburses 9% of net sales for five years, capped at Rs 30 crore per application.
3.Start-ups and MSMEs under the commercial design track can receive seed funding of up to Rs 15 crore or 50% of project cost, whichever is higher.
4.The Centre for Development of Advanced Computing (C-DAC) jointly owns the intellectual property developed under the strategic chip-design track.
Which of the statements given above are correct?
Consider the following statements about the eligibility conditions for the strategic chip-design track under Semicon 2.0:
1.Companies must be incorporated and headquartered in India.
2.Companies owned and controlled by Overseas Citizens of India (OCIs) are eligible, provided they maintain a significant operational presence in India.
3.Companies may work with global firms and research institutions in consortiums.
4.Intellectual property developed under this track is solely owned by the selected company.
Which of the statements given above is/are correct?
With reference to the royalty financing option under Semicon 2.0's commercial chip-design track, consider the following:
1.Eligible companies repay government assistance at 5% of net revenue from the supported product.
2.Repayment continues until 1.5 times the government assistance has been recovered.
3.This option is available only to start-ups and MSMEs, not to larger companies.
Which of the statements given above is/are correct?
Match the following capital expenditure support rates under Semicon 2.0 with the correct facility type:
List I (Facility Type) — List II (Capex Support Rate)
A.Large silicon wafer fabs — 1. 30%
B.Compound semiconductor and photonics fabs — 2. 35%
C.Advanced chip-packaging facilities — 3. 40%
D.Semiconductor equipment and materials manufacturing — 4. 35%
Which of the following is the correct matching?
Which of the following correctly describes the 'fabless' semiconductor company model that Semicon 2.0 primarily aims to promote?
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