S&TGS3

SEMICON India 2026 Concludes, Marks Shift to Semicon 2.0

PIB·2026-09-20· Read original

"SEMICON India 2026 Concludes, Marks Shift to Semicon 2.0"

Prelims Facts

  • •Semicon India 1.0 was launched in 2021 with an outlay of ₹76,000 crore.
  • •Semicon India 2.0, approved in 2026, has an outlay of ₹1,27,500 crore structured around six pillars.
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Key Terms

Fabrication (Fab)

a facility where semiconductor wafers are manufactured from raw silicon.

Advanced Packaging

technology that integrates multiple chips into a single package for better performance.

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Study Note

BackgroundCore Concept

Background

India's semiconductor push began as a follow-on to its electronics manufacturing success. Between 2014-15 and 2025-26, electronics goods production grew nearly sevenfold to reach ₹13.11 lakh crore, and India became the world's second largest mobile phone manufacturer by volume, with smartphones emerging as its single largest exported commodity in FY 2025-26. This manufacturing base created both the market demand and the industrial confidence to justify entering semiconductor fabrication, a capital-intensive sector previously dominated by a handful of countries.

The formal mission, Semicon India, was launched in 2021 as Semicon 1.0 with a ₹76,000 crore outlay covering chip design, fabrication, packaging, testing, equipment, materials and talent development. Twelve semiconductor projects were approved under this phase across six states, drawing investment commitments exceeding ₹1.64 lakh crore. The nodal body overseeing this effort is the India Semiconductor Mission (ISM), housed within the Ministry of Electronics and Information Technology (MeitY), which coordinates policy, incentive disbursal and industry engagement.

In July 2026, the government scaled up the mission to Semicon 2.0, with an outlay of ₹1,27,500 crore, structured around six pillars: chip design, semiconductor equipment and materials, new fabrication facilities, advanced packaging, research and development, and talent development. This second phase reflects a shift from proving that India can attract semiconductor investment to building depth across the entire value chain, not merely assembly and testing.

The Topic Explained

India's entry strategy has been deliberately phased. Rather than starting with the most advanced logic-chip fabrication nodes, the country first built capability where technological and capital barriers were lower: chip design services, assembly, testing, marking and packaging, and specialised or mature-node fabrication. This mirrors the earlier electronics assembly strategy, where India built scale in mobile phone assembly before deepening into component manufacturing.

Talent and design capability are supported through dedicated schemes. The Design Linked Incentive (DLI) Scheme provides financial support and access to Electronic Design Automation (EDA) tools for domestic chip design startups. …

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Practice MCQs

S&Tmedium

Consider the following statements regarding India's semiconductor mission:

1.Semicon India 1.0 was launched in 2021 with an outlay of ₹76,000 crore.

2.Semicon India 2.0 has an outlay of ₹1,27,500 crore structured around six pillars.

Which of the statements given above is/are correct?

A1 only
B2 only
CBoth 1 and 2
DNeither 1 nor 2
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S&Teasy

Which one of the following is NOT one of the six pillars of Semicon India 2.0?

AChip design
BAdvanced packaging
CAgricultural technology
DTalent development
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S&Teasy

Consider the following statements:

1.India is the world's second largest mobile phone manufacturer by volume.

2.Smartphones became India's single largest exported commodity in FY 2025-26.

Which of the statements given above is/are correct?

A1 only
B2 only
CBoth 1 and 2
DNeither 1 nor 2
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S&Tmedium

Match List-I (Programme/Institution) with List-II (Primary Function) and select the correct answer using the code given below:

List-I:

A.Design Linked Incentive (DLI) Scheme

B.Chips to Startup (C2S) Programme

C.India Semiconductor Mission (ISM)

List-II:

1.Nodal agency under MeitY for semiconductor policy

2.Trains students/entrepreneurs in chip design using indigenous processors

3.Provides financial incentive for domestic chip design startups

AA-3, B-2, C-1
BA-1, B-3, C-2
CA-2, B-1, C-3
DA-3, B-1, C-2
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